Pci Express Root Complex Drivers

 

Introduction

The PCI Express (PCIe) module is a multi-lane I/O interconnect providinglow pin count, high reliability, and high-speed data transfer at ratesof up to 8.0 Gbps per lane per direction. It is a 3rd Generation I/O Interconnecttechnology succeeding ISA and PCI bus that is designed to be used as ageneral-purpose serial I/O interconnect in multiple market segments,including desktop, mobile, server, storage and embedded communications.

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Features of J7ES

There are four instances of the PCIe subsystem. Following are some of themain features:

  • Each instance can be configured to operate in Root Complex mode orEnd Point mode
  • One or two lane configuration, capable up to 8.0 Gbps/lane (Gen3)
  • Support for Legacy, MSI and MSI-X Interrupt
  • There can be 32 different address mappings in outbound address translationunit. The mappings can be from regions reserved for each PCIe instance.
    • For instance PCIE0 and PCIE1, there are two regions in SoC Memory Map:
      • 128 MB region with address in lower 32 bits
      • 4 GB region with address above 32 bits
    • For instance PCIE2 and PCIE3, there are two regions in SoC Memory Map:
      • 128 MB region with address above 32 bits
      • 4 GB region with address above 32 bits

Capabilities of J721E EVM

There are three instances of the PCIe subsystem on the EVM. Following aresome of the details for each instance:

InstanceSupported lanesSupported Connector
PCIE01 laneStandard female connector
PCIE12 laneStandard female connector
PCIE22 lanem.2 connector keyed for SSD (M key)

Hardware Setup Details

J721E is, by default, intended to be operated inRoot Complex mode.

For End Point mode, PCIE_1L_MODE_SEL (switch 5) and PCIE_2L_MODE_SEL (switch 6)should be set to ‘0’.

RC Software Architecture

Following is the software architecture for Root Complex mode:

Following is a brief explanation of layers shown in the diagram:

  • There are different drivers for the connected PCIe devices likepci_endpoint_test, tg-3, r8169, xhci-pci, ahci, etc. It could bevendor-specific like most of the ethernet cards (tg3, r8169) or class-specificlike xhci-pci and ahci. Each of these drivers will also interact with it’s owndomain-specific stack. For example, tg3 will interface with network stack, andxhci-pci will interface with USB stack.
  • The PCI core layer scans the PCIe bus to identify and detect any PCIe devices.It also binds the driver from the layer above, for the PCIe device, based onvendorid, deviceid and class.
  • The PCI BIOS layer handles resource management. For example, allocation ofmemory resources for BARs.
  • The bottom-most layer consists of the PCIe platform drivers like pcie-cadence,pcie-designware, etc. pci-j721e and pci-dra7xx are TI’s wrappers over thesedrivers. They configure platform-specific controllers and performactual register writes.

RC Device Configuration

DTS Modification

The default dts for J721E is configured to be used inroot complex mode.

Linux Driver Configuration

The following config options have to be enabled in order to configure thePCI controller to be used in Root Complex mode.

Testing Details

The RC should enumerate any off-the-shelf PCIe cards. It has been testedwith Ethernet cards, NVMe cards, PCIe USB card, PCIe WiFi card, PCIe SATAcard and also to J721E in loopback mode.

In order to see if the connected card is detected, lspci utility should beused. Different utilities can be used depending on the cards.

Following are the outputs for some of them:

  • Loopback mode (J721E EVM to J721E EVM)

    Two J721E EVMs can be connected in loopback mode by following the stepsexplained inEnd Point (EP) Device Configurationsection for End Point (EP) andHOST Device Configurationsection for Root Complex (RC) inPCIe End Point documentation. The pci-epf-testdriver will be configured for End Point(EP) using those steps.

    The lspci output on the Root Complex (RC) device is as follows:

  • WiFi card

    • lspci output
    • Test using ping

  • NVMe SSD

    • lspci output
    • Test using hdparm
    • Test using dd

J7200 Testing Details

PCIe and QSGMII uses the same SERDES in J7200. The default SDK is enabled for QSGMII. In order totest PCIe, Ethfw firmware shouldn’t be loaded and PCIe overlay file should be applied.

The simplest way to avoid ethfw from being loaded is to link j7200-main-r5f0_0-fw to IPC firmware.

The following Device Tree Overlay should be applied for testing J7200 RC.

The following command should be given in u-boot to apply overlay

Author

Tom L Nguyen tom.l.nguyen@intel.com 11/03/2004

Copyright

© 2004 Intel Corporation

2.1. About this guide¶

This guide describes the basics of the PCI Express Port Bus driverand provides information on how to enable the service drivers toregister/unregister with the PCI Express Port Bus Driver.

2.2. What is the PCI Express Port Bus Driver¶

A PCI Express Port is a logical PCI-PCI Bridge structure. Thereare two types of PCI Express Port: the Root Port and the SwitchPort. The Root Port originates a PCI Express link from a PCI ExpressRoot Complex and the Switch Port connects PCI Express links tointernal logical PCI buses. The Switch Port, which has its secondarybus representing the switch’s internal routing logic, is called theswitch’s Upstream Port. The switch’s Downstream Port is bridging fromswitch’s internal routing bus to a bus representing the downstreamPCI Express link from the PCI Express Switch.

Express

A PCI Express Port can provide up to four distinct functions,referred to in this document as services, depending on its port type.PCI Express Port’s services include native hotplug support (HP),power management event support (PME), advanced error reportingsupport (AER), and virtual channel support (VC). These services maybe handled by a single complex driver or be individually distributedand handled by corresponding service drivers.

2.3. Why use the PCI Express Port Bus Driver?¶

In existing Linux kernels, the Linux Device Driver Model allows aphysical device to be handled by only a single driver. The PCIExpress Port is a PCI-PCI Bridge device with multiple distinctservices. To maintain a clean and simple solution each servicemay have its own software service driver. In this case severalservice drivers will compete for a single PCI-PCI Bridge device.For example, if the PCI Express Root Port native hotplug servicedriver is loaded first, it claims a PCI-PCI Bridge Root Port. Thekernel therefore does not load other service drivers for that RootPort. In other words, it is impossible to have multiple servicedrivers load and run on a PCI-PCI Bridge device simultaneouslyusing the current driver model.

To enable multiple service drivers running simultaneously requireshaving a PCI Express Port Bus driver, which manages all populatedPCI Express Ports and distributes all provided service requeststo the corresponding service drivers as required. Some keyadvantages of using the PCI Express Port Bus driver are listed below:

  • Allow multiple service drivers to run simultaneously ona PCI-PCI Bridge Port device.

  • Allow service drivers implemented in an independentstaged approach.

  • Allow one service driver to run on multiple PCI-PCI BridgePort devices.

  • Manage and distribute resources of a PCI-PCI Bridge Portdevice to requested service drivers.

2.4. Configuring the PCI Express Port Bus Driver vs. Service Drivers¶

2.4.1. Including the PCI Express Port Bus Driver Support into the Kernel¶

Including the PCI Express Port Bus driver depends on whether the PCIExpress support is included in the kernel config. The kernel willautomatically include the PCI Express Port Bus driver as a kerneldriver when the PCI Express support is enabled in the kernel.

2.4.2. Enabling Service Driver Support¶

PCI device drivers are implemented based on Linux Device Driver Model.All service drivers are PCI device drivers. As discussed above, it isimpossible to load any service driver once the kernel has loaded thePCI Express Port Bus Driver. To meet the PCI Express Port Bus DriverModel requires some minimal changes on existing service drivers thatimposes no impact on the functionality of existing service drivers.

A service driver is required to use the two APIs shown below toregister its service with the PCI Express Port Bus driver (seesection 5.2.1 & 5.2.2). It is important that a service driverinitializes the pcie_port_service_driver data structure, included inheader file /include/linux/pcieport_if.h, before calling these APIs.Failure to do so will result an identity mismatch, which preventsthe PCI Express Port Bus driver from loading a service driver.

2.4.2.1. pcie_port_service_register¶

This API replaces the Linux Driver Model’s pci_register_driver API. Aservice driver should always calls pcie_port_service_register atmodule init. Note that after service driver being loaded, callssuch as pci_enable_device(dev) and pci_set_master(dev) are no longernecessary since these calls are executed by the PCI Port Bus driver.

2.4.2.2. pcie_port_service_unregister¶

pcie_port_service_unregister replaces the Linux Driver Model’spci_unregister_driver. It’s always called by service driver when amodule exits.

2.4.2.3. Sample Code¶

Below is sample service driver code to initialize the port servicedriver data structure.

Express

Below is a sample code for registering/unregistering a servicedriver.

2.5. Possible Resource Conflicts¶

Since all service drivers of a PCI-PCI Bridge Port device areallowed to run simultaneously, below lists a few of possible resourceconflicts with proposed solutions.

Pci Express Root Complex Drivers Download

2.5.1. MSI and MSI-X Vector Resource¶

Pci Express Root Complex Drivers

Once MSI or MSI-X interrupts are enabled on a device, it stays in thismode until they are disabled again. Since service drivers of the samePCI-PCI Bridge port share the same physical device, if an individualservice driver enables or disables MSI/MSI-X mode it may resultunpredictable behavior.

What Is Pci Express Root Complex

To avoid this situation all service drivers are not permitted toswitch interrupt mode on its device. The PCI Express Port Bus driveris responsible for determining the interrupt mode and this should betransparent to service drivers. Service drivers need to know onlythe vector IRQ assigned to the field irq of struct pcie_device, whichis passed in when the PCI Express Port Bus driver probes each servicedriver. Service drivers should use (struct pcie_device*)dev->irq tocall request_irq/free_irq. In addition, the interrupt mode is storedin the field interrupt_mode of struct pcie_device.

2.5.2. PCI Memory/IO Mapped Regions¶

Service drivers for PCI Express Power Management (PME), AdvancedError Reporting (AER), Hot-Plug (HP) and Virtual Channel (VC) accessPCI configuration space on the PCI Express port. In all cases theregisters accessed are independent of each other. This patch assumesthat all service drivers will be well behaved and not overwriteother service driver’s configuration settings.

2.5.3. PCI Config Registers¶

Each service driver runs its PCI config operations on its owncapability structure except the PCI Express capability structure, inwhich Root Control register and Device Control register are sharedbetween PME and AER. This patch assumes that all service driverswill be well behaved and not overwrite other service driver’sconfiguration settings.